1. Field of the Invention
The disclosure relates in general to a three-dimensional (3D) semiconductor device and a method of manufacturing the same, more particularly to a 3D semiconductor device with bottom contacts and a method of manufacturing the same.
2. Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable thin-film transistor (TFT) NAND-type flash memory structures have been proposed. Various semiconductor devices with three-dimensional (3D) stacked structures, having single-gate unit cells, double gate unit cells or surrounding gate unit cells, have been provided.
It is desirable to develop a semiconductor device with 3D stacked structure not only with larger number of multiple planes being stacked to achieve greater storage capacity, but also with memory cells having excellent electrical properties (such as reliability of data storage and speed of operation), so that the memory cells can be erased and programmed effectively. Typically, NAND Flash page size is proportional to the number of the bit lines (BL). Accordingly, when the device is scaled down, not only the decreased cost but also the increased read/write data rate are achieved due to the increasing of parallel operation, which leads to higher data rate. However, there are still other issues needed to be considered when the device is scaled down.
Take a 3D vertical channel (VC) semiconductor device (ex: NAND) for example, the X-pitch of the multilayered connectors can be relaxed by the wide staircase rule, but the Y-pitch would be very tight in order to connect the multilayered connectors to the word line decoder. Although enlarge block_Y may relax y-pitch, the number of the string selection line (SSL) will be increased, which induce more issues of power consumption and signal disturbance. Considering the serious disturbance mode in 3D NAND, less NSSL (number of SSL) design would be better choice for constructing the 3D device. However, this may induce high pattern density in the layer (WL) fan out area.